This invention relates to the processing of thin wafers, such as slices of semiconductor silicon and, more particularly, to improved method and apparatus for mounting of such thin slices on a carrier for performing of mechanical operations thereon, such as polishing of the wafers.
This invention constitutes an improvement of the inventions disclosed and claimed in Walsh U.S. Pat. Nos. 3,475,867 and 3,492,763.
The former discloses a method of wax mounting of semiconductor slices, e.g., silicon to a carrier plate having a flat surface. After the wafers have been mounted on the carrier plate, they are subjected to operations including washing, lapping, polishing, etc. The arrangement disclosed in the latter patent provides for the location of the wafers upon the carrier surface in a uniform arrangement to eliminate deleterious effects of random slice disposition.
When utilizing the methodology as described in the above-identified patents for the wax mounting of silicon wafers to carrier plates for further operations thereon, and particularly polishing to a high degree of surface perfection as appropriate for the manufacture of integrated circuits in such wafers, it has been observed that there is approximately a 10% incidence of air bubble entrapment in the wax layer under the slice, even though entrainment of air bubbles was sought to be avoided by the use of such prior art methodology. Such entrapment is believed to happen when, for example, the concave surface of a wafer which is bowed by virtue of strain therein resulting from sawing or other factors is placed in contact with the sticky wax layer which is first applied to the carrier plate. If the edges of the wafer, or slice, are, in effect "wetted" by the wax before all of the air is forced out from beneath it by the pressure applied against the wafer as it is pressed against the wax coating, then some air remains trapped beneath the slice i.e., between the wafer and adjacent surface of the carrier plate.
Such entrapped air bubbles are a matter of concern when the wafers must be polished to a state of extreme flatness. In the manufacture of very large scale integrated (VLSI) circuits, the density of circuit elements which must be created on a silicon wafer requires an extraordinarily high order of precision and resolution calling for wafer flatness heretofore not required. The necessary polished slice flatness for such applications (less than about 2 micrometers peak-to-valley) cannot be achieved if significant air bubbles are entrapped between a wafer and a carrier and are permitted to remain during polishing. Such bubbles provide a source of pressure tending to bow out a portion of the wafer over the bubble. Accordingly, the pressure exerted by the bubble during polishing results in a region which is polished under slightly greater pressure than portions of the wafer which do not have bubbles therebeneath. Consequently, the polished wafer has regions of thinness after polishing where the bubbles were present.